1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device that is insensitive to a change in a voltage, circuit dimension or temperature, and provides for a rapid read data operation.
2. Description of the Related Art
With the demand for semiconductor devices with increased speed, clock frequencies of the semiconductor devices increase and time intervals between signals decrease.
Also, as the amount of time necessary for data read and write operations decreases, more accurate data read and write operations are required.
In particular, in the case of semiconductor devices, a sufficient time margin between a read signal and a sampling signal is required to amplify a data signal to a required voltage. However, the margin may change with a power supply voltage or temperature. Thus, if the time intervals are set sufficiently large in consideration of a change in the power supply voltage or temperature, the overall data read time and data write time increase.
FIG. 1 illustrates a conventional data input/output (IO) sense amplifier (S/A) 100.
The data IO S/A 100 includes a voltage IO S/A 101, a first read signal (FRP) generator 102, and a tri-state driver controller 103.
Small signal data SGIO and /SGIO output from a memory cell (not shown) are input to the voltage IO S/A 101. The voltage IO S/A 101 amplifies the small signal data SGIO and /SGIO to data IO and /IO that are sufficiently large to be outputs of a complementary metal-oxide semiconductor (CMOS) voltage level, samples the amplified data in synchronization with an FRP, and outputs the sampled data.
The FRP generator 102 receives an external clock signal CLK, generates the FRP, and outputs the FRP to the voltage IO S/A 101 and the tri-state driver controller 103.
The sampled data IO and /IO output from the voltage IO S/A 101 are input to the tri-state driver controller 103, and the tri-state driver controller 103 outputs pull-up data PU and pull-down data PD that are then output to an external device as a data output signal DOUT.
In such a conventional voltage IO S/A, an absolute time margin that facilitates a successful data read operation with just one sampling operation is required.
FIG. 2 is a timing diagram illustrating a conventional method of driving the voltage IO S/A 101.
Once a column selection line CSL is enabled, the small signal data SGIO and /SGIO are amplified. If the small signal data SGIO and /SGIO are amplified to an amplitude of about 100 mV so as to be accurately read, the FRP is enabled and the small signal data SGIO and /SGIO are sampled once in synchronization with the FRP.
In the voltage IO S/A 101 of FIG. 2, since the data read operation should be successful with one sampling operation as described above, an absolute time margin between an enable signal of the column selection line CSL and an enable signal of the FRP is required. This sufficient margin should be large enough to amplify the small signal data SGIO and /SGIO to a sufficient amplitude (about 100 mV). If sampling is performed when the time delay between the column selection line CSL and the FRP is small and the small signal data SGIO and /SGIO are amplified to less than the sufficient amplitude, the data read operation may fail.
However, in semiconductor devices, characteristics of the sufficient margin are very sensitive to changes in a process, a power supply voltage and temperature (PVT). For example, if a power supply voltage VDD increases, the time delay between the column selection line (CSL) and the FRP decreases.
FIG. 3 is a graph illustrating a change in a margin between the column selection line (CSL) and the FRP with respect to a power supply voltage.
Referring to FIG. 3, as the power supply voltage VDD increases, the time interval required to enable the column selection line (CSL) decreases. More specifically, the column selection line (CSL) is enabled in 9.033 ns when the power supply voltage VDD is 1.6V and is enabled in 5.378 ns when the power supply voltage VDD is 2.5V. Also, as the power supply voltage VDD increases, the time interval required to enable the FRP decreases. More specifically, the FRP is enabled in 12.284 ns when the power supply voltage VDD is 1.6V and is enabled in 7.221 ns when the power supply voltage VDD is 2.5V.
Also, as the power supply voltage VDD increases, the margin between the column selection line CSL and the FRP decreases. When the power supply voltage VDD is 1.6V, the margin is about 3.251 ns. However, when the power supply voltage VDD increases to 2.5V, the margin decreases to 1.843 ns.
TABLE 1VDD (V)CSL (ns)FRP (ns)Margin (ns)1.69.03312.2843.2511.78.28511.2642.9791.87.64510.3522.7071.97.1289.6572.5292.06.6709.0232.3532.16.3978.6162.2192.26.0718.1522.0812.35.8077.7851.9782.45.5927.5061.9142.55.3787.2211.843
It can be seen from Table 1 that the margin between the column selection line CSL and the FRP decreases as the power supply voltage VDD increases. In this case, if the sufficient margin is secured at a high voltage, a semiconductor device operates at a proper speed at a high voltage, but the margin between the column selection line CSL and the FRP unnecessarily increases at a low voltage. As a result, a speed of the data read operation in the semiconductor device decreases according to the increase in the margin.
On the other hand, if the sufficient margin is only secured at a low voltage, the semiconductor device operates at a proper speed and flawlessly reads data at a low voltage, but a sufficient time delay between the column selection line (CSL) and the FRP is not secured at a high voltage. As a result, an error may occur in the data read operation.
FIG. 4 is a timing diagram illustrating the operation of the conventional voltage IO S/A 101 when the power supply voltage is increased.
Referring to FIG. 4, a margin 401 between the column selection line CSL and the FRP at a low voltage is greater than a margin 402 between them at a high voltage. Thus, if the characteristics of the sufficient margin is based on a low voltage, the small signal data SGIO and /SGIO are amplified to a voltage 403 sufficient to read data over the margin 401. However, at a high voltage, the small signal data SGIO and /SGIO are amplified to a voltage 404 that is insufficient to read data. In this case, an error may occur in the data read operation.
The margin between the enable signal of the column selection line CSL and the enable signal of the FRP signal may change as a result of an inconsistent circuit dimension (CD). Inconsistencies in the circuit dimension occur due to an error in the length of a transistor formed during a semiconductor device manufacturing process or due to a circuit length difference between memory cells to voltage IO S/A 101.
TABLE 2CD VARMARGIN(um)CSL (ns)FRP (ns)(ns)0.049.89713.6473.7500.039.72813.3613.6330.029.44512.9663.2510.019.23912.5543.31509/03312.2843.251−0.018.88012.0323.152−0.028.59411.6753.081−0.038.35311.3563.003−0.048.12210.9682.846
It can be seen from Table 2 that the time delay between the column selection line CSL and the FRP decreases as the circuit dimension CD decreases.
Thus, if the sufficient margin is based on a small circuit dimension, the amount of time required for the data read operation unnecessarily increases in a large circuit dimension. Furthermore, if the sufficient margin is based on a large circuit dimension, an error may occur in the data read operation in a short circuit dimension.